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Google Static Timing Analysis Engineer FullChip/ASIC Implementation United States, California, San Diego 750640808
14.04.2025
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Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: San Diego, CA, USA; Mountain View, CA, USA.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of technical experience in silicon timing closure and chip integration.
- Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
- Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Experience with high complexity silicon in state-of-the-art technology process nodes.
- Experience with ASIC design flows and methodology of static timing analysis.
- Effective skills with scripting languages such as Tcl or Perl.
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