Microsoft Design Verification Engineer 

United States, California, Mountain View 

749316214

Required Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

  • OR 4+ years technical engineering experience.

• 3+ years of experience in developing test plans, creating simulation environments, developing tests, and debugging for multiple IPs, SoCs or systems.
• Proficient in SystemVerilog, C/C++, and scripting languages such as Python, Ruby or Perl.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:
  • This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred/Additional Qualifications:

• 5+ years technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• In depth knowledge of verification principles, testbenches, stimulus generation

• Substantial background in creatingUVMenvironments, developing tests, and debugging designs.

• Solid understanding of chip and/or computer architecture.

• Experience writing tests in C and C++.

• Scripting language such as Python, Ruby, or Perl.

• Experience with secure hardware design for embedded systems.

• Experience with hardware emulation or FPGAs.

• Experience in RTL design for FPGA or emulation.

• Experience in Assembly,start upcode and linker scripts.

• Experience in developingmakefilesfor software development.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until December 24, 2024.

• Plan the verification of complex design IP interacting with the architecture and design engineers to identify verification test scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Develop tests using UVM or C/C++.
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage to plug verification holes and meet tape out requirements.
• Embody our