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Google SoC RAS Design Tech Lead Machine Learning Accelerators United States, California, Sunnyvale 748669700
18.09.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- 3 years of experience working with system and hardware teams in defining the RAS requirements and architecture.
- Experience in computer architecture, logic design and leading block or subsystem level RTL development.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- 12 years of experience in SOC architecture and design, including 6 years of experience architecting and designing RAS features.
- Experience of SOC subsystem level logic redundancy design and test architecture.
- Understanding of circuit level SER (Soft Error Rate) modeling, measurement and mitigation techniques.
- Understanding of error coding techniques and design experience of ECC implementations.
- Understanding of SDC, DUE and DCE, and associated metrics, analysis and calculations.
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