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What you’ll be doing:
Micro-architecture definition for System-level modules
RTL design, synthesis, timing.
Silicon bring-up.
Chip level integration.
What we need to see:
BS / MS or equivalent experience in Microelectronics/ Electronic Engineering/ Computer Science and related or equivalent experience.
4+ years of ASIC design experience.
Hold a basic sense of verification methodology.
Understand frontend ASIC design flow including RTL design, synthesis and timing analysis.
Excellent analytical and problem-solving skills.
Fluent English (both written and spoken) and excellent communication skills.
Good team work spirit, easy to cooperate with team members.
Ways to stand out from the crowd:
Broad knowledge with GPU techniques, PCIE, SOC architecture and Computer architecture is a big plus.
Strong programming skills in C/C++, SystemVerilog and Perl script is appreciated as a plus.
Familiar with DFT and ATE flow will be also be a plus
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