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Google Manager II Silicon Digital Design United States, California, Mountain View 745521230
Yesterday
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- 4 years of experience in people management, developing employees.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
- Experience with a scripting language like Perl or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
- Domain knowledge in Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset.
- Knowledge of ASIC Verification, DFT, synthesis, STA, or Physical Design.
- Knowledge of high performance and low-power design techniques.
- Knowledge of FPGA and emulation platforms.
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