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Google RTL Design Engineer 
India, Karnataka, Bengaluru 
740011756

08.04.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
  • 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture
  • Experience with ARM-based SoCs, interconnects and ASIC methodology

Preferred qualifications:
  • Master’s degree in Electrical Engineering or Computer Engineering
  • 3 years of experience with IP design for clocking, interconnects, peripherals
  • Experience with methodologies for low power estimation, timing closure, synthesis
  • Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC)