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Apple PLL Design Engineer 
United States, California, Cupertino 
738394638

02.05.2024
Key Qualifications
  • The ideal candidate should have confirmed taking chips to production with experience in the following areas: Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs, Digital PLL techniques, etc
  • High speed digital circuit design and analysis
  • High frequency signal integrity experience
  • Experience with LC and RO VCO design. Good knowledge of band gaps, bias, op-amps, LDOs, feedback and compensation techniques as well as digitally assisted analog circuit techniques
  • Lab and ATE test plans, measurement for characterization, and volume production.
Description
Understand system level requirements to build overall PLL specifications.Build behavioral models of PLL to drive architectural decisions and derive block-level requirements for analog and digital blocks.Complete top-level spice and mixed-mode simulations to validate top-level integration.Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.Define production/bench-level test plans for post-silicon characterization.Work with lab engineers in taking lab measurements to validate IP.Review ATE and lab test results to resolve yield issues and drive bug fixes.Hold design reviews of blocks with peers/management to show design meets spec targets and requirements.
Education & Experience
BSEE with minimum 10 years of experience
Pay & Benefits
  • At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $170,700.00 and $300,200.00, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.