Understand system level requirements to build overall PLL specifications.Build behavioral models of PLL to drive architectural decisions and derive block-level requirements for analog and digital blocks.Complete top-level spice and mixed-mode simulations to validate top-level integration.Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.Define production/bench-level test plans for post-silicon characterization.Work with lab engineers in taking lab measurements to validate IP.Review ATE and lab test results to resolve yield issues and drive bug fixes.Hold design reviews of blocks with peers/management to show design meets spec targets and requirements.