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Apple Wireless SoC Low Power Design Engineer United States, California, San Diego 722695899
02.05.2024
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Key Qualifications
- 5+ years of experiences in Low Power ASIC design and SOC integration
- Proficiency in ASIC logic design
- Extensive experience with SoC power management design including power gating, isolation, retention and DVFS techniques
- SoC level clock mesh / reset design experience desirable
- Proficiency in scripting languages (Shell and Perl highly desirable, Python skills are a plus)
- Deep understanding of ASIC low power design techniques, e.g. Power analysis, UPF, VCLP
- Hands on experience with PTPX and Power Artist power analysis tools is a plus
- System architecture knowledge is a bonus
- Silicon validation / power measurement experience is a plus
Description
- Drive SoC low power micro-architecture, definition, implementation, and analysis- Own complex SoC power management, boot flow, clock and reset management- Write micro-architecture specifications and design specifications- Design, implement, and debug complex logic designs- Integrate complex IPs into SoC- Run tools to ensure lint-free and CDC clean design- Support all front end design and integration activities such as synthesis and timing constraints- Support pre and post silicon validation
Education & Experience
BS and 3+ years of relevant industry Experience
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $131,500.00 and $243,300.00, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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