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Google Physical Design Engineer Static Timing Analysis United States, California, Sunnyvale 722128310
25.02.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- 5 years of experience in the domain of static timing analysis. (i.e., constraint authoring and verification, static timing analysis and timing ECO creation).
- Experience with EDA tools (i.e. Primetime or Tempus) and EDA Tcl commands (i.e., for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk).
Preferred qualifications:
- 8 years of experience in the domain of static timing analysis.
- Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Knowledge of semiconductor device physics, SPICE simulation and complex static timing topics, including complex clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification.
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