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Google Senior Staff Physical Design Engineer 
United States, California, Sunnyvale 
720409808

24.06.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years experience in ASIC physical design flows and methodologies in advanced process nodes.
  • Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools).
  • Scripting experience with Python, Tcl, or Perl.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience leading one or more aspects of physical design and working with IP integration (memories, IO’s and Analog IP).
  • Experience solving physical design challenges across various technologies (e.g., embedded processors, DDR, networking fabrics, etc.).
  • Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation.
  • Knowledge of semiconductor device physics, transistor characteristics, and SystemVerilog/Verilog.