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Cisco Senior DFT Engineer United States, California, San Jose 719585355
18.11.2024
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Who You'll Work With
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.
What You'll Do
- Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards
- Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead junior engineers to deliver expected implementations on schedules
Minimum Qualifications:
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 8 years of experience.
- Prior experience with the latest innovative trends in DFT, test and silicon engineering.
- Prior experience with scripting languages, Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Prior experience with hardware design specifications and verification plan/matrix, RTL & testbench implementations.
- Prior experience on DFT quality sign off checklist and reviews for chip tape out, including test coverage, STA.
- Prior experience pre-silicon DFT implementation and verification flows, and post-silicon test bring up procedures.
Preferred qualifications:
- DFT CAD development – Test Architecture, Methodology and Infrastructure
- Post silicon validation using DFT patterns.
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