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Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
1-3 years experience in Digital ASIC / Processor Design
Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process TechnologyStrong communication skills to work with design teams worldwideExtensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECOExtensive experience in UPF based power intent and synthesisHigh-speed and Low-power 5G and WLAN Modem Hardmacro Implementation Lead- Lead, train and mentor team of junior engineers to execute on a complex project for a large modem design in advanced process nodes- Work closely with RTL, DFT and PD leads worldwide to take a project from Post-RTL to Netlist release, and converge on area, timing, power and testability- Primary tasks include writing timing constraints, synthesis, formal verification, CLP, Primetime, PTPX, CECO- Optimize datapath design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.- Optimize PPA using the right tool options and stdcell libraries / memories- Handle complex digital blocks with >1M gates in advanced process nodes from 4nm / 5nm / 7nm / 8nm
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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