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What you'll be doing:
Innovate on 3D-IC Heterogenous integration as a comprehensive co-optimization from System to Silicon in partnership with domain experts.
Establish 3D-IC prototypes across market segments. Collaboration with Product teams to identify critical product characteristics and target setting requirements.
Engage with EDA providers on 3D-IC EDA feature requirements and 3D-IC design methodology.
Design optimization of 3D advanced silicon/package technology features to enable strong product differentiation.
Design analysis and optimization for 3D-IC Advanced Silicon and Packaging technology definition and certification.
3D-IC Test Chips validation of 3D-IC technology platforms and design methodology.
What we need to see:
MS or PhD degree in Electrical or Computer Engineering (or equivalent experience)
Minimum of 5+ years' experience in 3DIC, interposer and package design.
Deep understanding and experience driving digital design flows and EDA vendor engagement.
Experience with Testchip designs and/or Product designs.
Multiple clock domain and Low Power Design.
Expertise with Python, TCL
Enjoy working with multiple levels and teams across organizations.
Effective verbal/written communication, and technical presentation skills
Self-starter with passion for growth, real enthusiasm for continuous learning and sharing findings across the team.
Ways to stand out from the crowd:
Familiarity with Machine Learning/Deep Learning
Experience in other Physical Design methodologies such as P&R, DFT, STA etc.
You will also be eligible for equity and .
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