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Job Description
Key technology areas of experience: wafer to wafer bonding - including fusion and hybrid bonding, complex heterogeneous wafer level packaging, TSV, die to wafer bonding, advanced substrate and chip on wafer stacking.
Prefer a PhD in Materials Science or Electrical Engineering with a semiconductor focus.
Will work in the fabrication and development of BEOL processes and wafer level packaging. Experience should include end to end technology development including: process assumptions, ground rule generation, test site coordination and tape out, test site scheduling, setup and installation, route pipe cleaning, wafer processing logistics, test and characterization and process debug.
Key technology areas of experience: wafer to wafer bonding - including fusion and hybrid bonding, complex heterogeneous wafer level packaging, TSV, die to wafer bonding, advanced substrate and chip on wafer stacking.
Functional Knowledge
Leadership
Problem Solving
Impact
Interpersonal Skills
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