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What you'll be doing:
Lead and mentor a team of engineers in developing mixed-signal chips
Supervise the planning and specification of algorithms, evaluating PPA (Power, Performance, Area) trade-offs
Guide the design of digital circuits such as filters and analog calibration circuits
Ensure verification of digital designs using direct and random testing methodologies
Lead front-end design flows(Lint/CDC/Synthesis/DFT/LEC/STA)
Drive silicon bring-up efforts and performance optimization
Collaborate with multi-functional teams to align technology roadmaps with business objectives
Establish and maintain standard methodologies for mixed-signal design and verification
What we need to see:
M.S. or Ph.D. in Electrical Engineering or equivalent experience and over 8 years of overall experience in mixed signal
Proven experience in mixed-signal chip design, with 3+ years in a leadership role
Expertise in Verilog or SystemVerilog, logic design, and circuit modeling in RTL for mixed-signal blocks
Strong background in custom digital circuit design and adaptation algorithms (FFE, DFE, CTLE, CDR, offset cancellation), understanding of high-speed SerDes I/O digital design, with knowledge of protocols like Ethernet and PCIe
Experience with industry-standard verification methodologies, such as UVM
Proficiency with static timing and formal verification tools
Excellent communication and leadership skills, with the ability to drive technical strategy
You will also be eligible for equity and .
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