Qualcomm STA/Timing Engineer 

India, Karnataka, Bengaluru 

705069940

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

Overview: Experienced STA/Timing Engineer with 6-8 Years of hands-on experience on timing sign off/convergence for complex SOCs. Ability to start immediately on timing analysis/sign-off with PD/Methodology teams across multiple sites and different technology nodes.

Job Description

Responsibilities:

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.

• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.

• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.

• Evaluate multiple timing methodologies/tools on different designs and technology nodes.

• Work on automation scripts within STA/PD tools for methodology development.

• Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment

• Experience in design automation using TCL/Perl/Python.

• Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus

• Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.

Preferred Qualification/Skills

• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling

• Hands-on experience with STA tools - Prime-time, Tempus

• Have experience in driving timing convergence at Chip-level and Hard-Macro level

• In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

• Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)

• Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.

• Proficient is scripting languages – TCL, Perl, Awk

• Basic knowledge of device physics

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.