Qualcomm DFT Engineer 

United States, California, San Diego 

701731760

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre, and post-silicon in the DFT domain.

Preferred Qualifications

• 5+ years industry experience in the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs. A strong fundamental knowledge of DFT is required

• Understanding of core-based test methodology and scan isolation.

• Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.

• Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.

• Experience with industry EDA ATPG and insertion tools.

• Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$134,500.00 - $201,500.00