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Google RTL Design Lead Silicon India, Karnataka, Bengaluru 696207200
24.07.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with digital design in ASIC.
- 4 years of experience in people management.
- Experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience with ARM-based SoCs, interconnects, and ASIC methodology.
Preferred qualifications:
- Master’s degree in Electrical Engineering or Computer Engineering.
- Experience with methodologies for low power estimation, timing closure, and synthesis.
- Experience leading IP/SoC design team for low power SoCs.
- Ability to drive a multi-generational roadmap for IP/SoC development.
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