- Developing and supporting new methods of editing or manipulating RTL and validating that these edits are correct by construction.
Minimum requirement of Bachelors Degree +10 years of relevant industry experience
Experience in programming languages such as Perl or Python
Experience in Verilog/System Verilog
Demonstrated experience driving large-scale software system development from specification to deployment
Demonstrated ability to take a spec, create software to meet it, develop the tests to validate the software, document the software, and support it with your customers
Experience in RTL (Verilog, SystemVerilog, and possibly VHDL)
Experience in memory bist or scan DFT
Excellent communication skills (both oral and written)
Good social skills and previous customer support
Experience with JSON or YAML is a plus
Experience in CI/CD automation is a plus
TCL experience is a plus
Experience in automated code testing infrastructure is a plus
Advanced usage of different source control tools like Perforce or Git is a plus