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What you’ll be doing:
Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl)
RTL design, synthesis, timing
Silicon bring-up
SOC level integration
What we need to see:
BS / MS in Microelectronics/ Electronic Engineering/ Computer Science and related (or equivalent experience).
2+ years of ASIC design experience or SOC integration design / flow experience
Hold a basic sense of verification methodology
Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis
Excellent analytical and problem-solving skills and an excellent attention to detail.
Good team work spirit, easy to cooperate with team members
Ways to stand out from the crowd:
Familiarity with ARM CPU and SoC system architecture, microprocessor, and microcontroller fundamentals (caches, buses, memory controllers, DMA, etc.)
Strong hands on competence in programming (C/C++) and scripting (Perl/Python). Exposure to System Verilog, SystemC/TLM is a strong plus.
You will also be eligible for equity and .
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