ARM STA Constraints Lead 

United States, California, San Diego 

693555210

• Owning full chip and block level timing closure ownership throughout the entire project cycle
• Handling timing constraints for functional and test mode at different logical hierarchical levels
• Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs
• ECO generation at both block and top level, handshaking with team for timing/functional ECO implementation

• Experience in developing and validating timing constraints for complete soc and also for blocks
• Experience in STA tools and handling different validation tools
• Knowledge of timing corners/modes, process variations and signal integrity related issues
• Work experience on timing closure for different power domain critical blocks
• Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors
• Work experience of 6-12 years in Synthesis and Timing constraints
• Must have worked on constraints development and timing closure on 5nm or 3nm technologies
• Strong Automation(Pert/Tcl/Python) and conversational abilities

• Bachelors in Electronics Engineering
• Coding skills in Per/Python or TCL or an equivalent language
• Good exposure in power aware synthesis for block and top level
• Familiarity with synthesis, logic equivalence, DFT, CLP and backend related methodology and tools
• Strong presentation skills

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding.

• Partner and customer focus
• Teamwork and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises