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Job Area:
Engineering Group, Engineering Group > Hardware Engineering
Develop RTL for multiple logic blocks of a DSP core
Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.
Job Function
This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage.
Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including:
functional and structural RTL design, design partitioning,
Experience with the following area is highly desirable:
Strong processor architecture knowledge
Microarchitecture implementation
Microprocessor integration
Low power design
Responsibilities
Develop RTL for multiple logic blocks of a DSP core
Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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