Intel E-Core CPU Design Automation Engineer 

Malaysia, Penang 

69123214

Job Description:

• Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.

• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.

• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.

• Optimizes CPU design to improve product level parameters such as power, frequency, and area.

• Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

Candidate must have aBachelor's degree inElectronic/Electrical/ComputerEngineeringwith
5+ years of experiencein :

• Deep understanding of most, if not all Physical Design and Verification Tools, Flows and Methods used in VLSI back-end custom-transistor based designs.

• Expertise using industry standard Engineering Design Automation (EDA) VLSI tools from 1 or more of Synopsys, Cadence and/or Mentor Graphics in one of more of the following areas of: STA, Power, ECO, LVS, Power-rail integrity, Noise and/or ERC flows.

• Deep understanding and experience of signoff aspects in STA for timing closure (OCV, constraints, parasitics), LVS, Static Power Analysis or Signal integrity analysis (Noise, SI-crosstalk).

• Familiar with digital custom circuit transistor-level designs and topologies including dynamic circuit techniques and memories as well as SPICE models and netlists.

• Desire to deep-dive into timing paths, perform QOR difference analysis and identify key issues.

• Expertise with Linux environments and basic shell scripting.

• Expertise is a must in 1 or more scripting languages such as Python, Perl and/or Tcl.

• Knowledge in standard-cell liberty format syntax and digital circuit device-level SPICE modelling.

• Knowledge in standard formats from 1 or more of transistor-level netlist, standard parasitic formats and/or SDC constraints.

• EDA tool API coding.

• Experience with advanced programming data structures.

Experienced HireShift 1 (Malaysia)Malaysia, Penang

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.