Minimum of 8 years of experience in hardware architecture, hardware design, or system engineering in data plane systems (including but not limited to L2/L3, MAC, protocol processing, or networking subsystems).
Proven hardware-centric mindset with strong attention to detail.
Solid technical breadth across HW/SW interfaces, protocol layering, and performance trade-offs.
Hands-on experience in system-level analysis, modeling, and optimization.
Capable of writing, reviewing, and owning engineering requirement specifications.
Experience in system integration and cross-functional collaboration.
Strong teamwork and communication skills, both written and verbal.
Fluent in English, with the ability to lead technical reviews and author high-quality documents.
BS or MS in Electrical Engineering, Computer Engineering, or a related field.
Familiarity with cellular data plane protocols (4G/5G), including SDAP, PDCP, and QoS handling.
Experience with SoC architecture and validation for data plane or communications systems.
Understanding of IP networking and protocol stacks, including packet flow classification and QoS enforcement.
Working knowledge of the PHY layer to ensure coh
erent L2-PHY integration and interface definition.
Experience with Python and/or C/C++ for modeling, simulation, or algorithm development.
Prior involvement in lab testing, silicon bring-up, and use of hardware validation tools and equipment.
Advanced degree (MS or PhD) in Electrical or Computer Engineering.