Microsoft Senior Validation Engineer 

United States, California, Mountain View 

688085957

Senior Validation Engineerto work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. You will be part of the Post-Silicon Validation team, driving many facets of high performance, high bandwidth designs.

Required Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 6+ years of experience in pre-silicon and post-silicon validation with a track record of delivering high performance Central Processing Unit (CPU), Vector processors and Graphics Processing Unit (GPU’s) or relevant experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Hands on experience with validation for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and developing tools for pre-silicon and post-silicon environments.
• Good programming skills in C/C++, Assembly, Python and scripting.
• Awareness about Post-silicon system level debug using windows system, chip Input Output (IO) interfaces, firmware hardware handshake and using analyzer/exerciser equipment.
• Knowledge of advanced computer architecture, boot flow, stress workload scenarios, performance, power and security.
• Experience with high/low speed IOs and industry standard bus/parallel/serial protocols like Ethernet, Peripheral Componenet Interconnect Express(PCIE),Joint Test Action Group(JTAG), Advanced eXtensible Interface(AXI). Advanced High-performance Bus(AHB) and I2.
• Good communication skills, team player, self-driven and problem solving ability.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

• Lead key components of post silicon functional validation of complex Application Specific Integrated Circuits(ASIC) System on Chip (SOC).
• Define testing strategies for Pre-Silicon Emulation,Field-Programmable Gate Array(FPGA)and Post-Silicon validation and achieve its goals.
• Work with Cross functional teams, Architecture, Design, Verification, Partner teams for project execution and also influence next generation designs.
• Develop Test plan, C tests and tools infrastructure to complete functional validation of complex design and report bug/issues.
• Running tests, debugging failures, creating stress and performance scenarios to meet test plan goals.
• Actively participate in chip bring up and write test firmware to support various teams.
• Innovate to improve validation efficiency through methodologies and tools.
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.
• Other
  • Embody our and