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Minimum Qualifications:
BE/Btech/MTech with 6 Plus years of experience
Preferred Qualifications:
Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
OVM/UVM, System Verilog, constrained random verification methodologies.
The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
Create plans and tests for validating portions of a complex microarchitecture using written specs, RTL code, Firmware and other tests as a guide
Experienced with the architecture, microarchitecture and Power Management flows and debugging failures to the root cause
Develop and utilize various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
Participate in the debug of failures on silicon and develop new testing strategies to detect these failures on RTL models
Develop tools and methods to streamline validation of PM flows, PM HW/FW interactions, and SOC level validation to deliver highest quality design in shortest time possible.
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