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Job Description:
1) Place and Route, CTS, channel analysis with respect to routing and congestion
2) Capable of handling big designs. Understanding of packaging, bonding, and top-level requirements
3) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, (chip finishing and Tapeout)
4) Integration of analog blocks, Meeting RC requirements for manual/special signals.
5) Good understanding of calibre rule deck of DRC/LVS/DFM,DFY, ERC and ESD latchup.
6) Good scripting knowledge perl and TCL, familiar with caliber, Innovus,
7) Understanding of VLSI fabrication process,
8) Implementing ECOs. Implementing IR/IVD fixes, SPEF extraction, signal EM and Noise fixes.
9) Responsible for all the integrity checks and post Tapeout eJob view release,
10) Open to new responsibilities in context of rapid technological change.
11) Good communication skills, work closely with the team members to accomplish PD milestone.
12) Secondary competencies :- Good understanding of CTS, STA, PTSI and timing.
Relevant experience of CAD tools cadence Innovus, Calibre is preferred.
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