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Google RTL Design Engineer Security Silicon India, Karnataka, Bengaluru 667333938
27.01.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- 3 years of experience designing Register Transfer Level (RTL) digital reasoning using SystemVerilog for Field-programmable Gate Array (FPGA)/Application-specific integrated circuits (ASICs).
- Experience with Application-specific integrated circuits (ASIC) design methodologies and QA flows (e.g., VCLP, Lint, CDC, RDC, SGDFT).
- Experience with a scripting language such as Perl or Python.
- Experience in area, power and performance optimization.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on Computer Architecture, or a related field.
- Experience with Unified Power Format (UPF) and VCLP.
- Experience in design and development of security blocks or crypto blocks.
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