The application window is expected to close by: 11/19/2024.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This is an onsite role and will require working out of the Milpitas/San Jose office location.
Your Impact
- Be part of the development organization as an ASIC Design Engineer with primary focus on RTL Design
- Create micro-architecture specifications and participate in reviews
- Implement Verilog RTL to meet timing and performance requirements
- Help define, evolve, and support our design methodology
- Collaborate with the verification team on as-needed basis to address design bugs and close code coverage
- Work closely with physical design team to close design timing and place-and-route issues
- Triage, debug, and root cause simulation, software bring-up, and customer failures. Perform diagnostic and post silicon validation tests in the lab
Minimum Qualifications:
- Bachelor's degree in Electrical or Computer Engineering and 4+ years of related work experience; Master’s Degree in EE and CE and +3 years of related experience; PH.D. in EE and CE and 0 years of related experience
- Prior experience with Verilog/System Verilog programming skills
- Prior experience with simulators/synthesis/static timing constraints and related tools
- Knowledge of verification methodologies and flow
- Knowledge of interactive and waveform debug skills
Preferred Qualifications:
- Understanding of Networking technologies and concepts
- Experience with ARM protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU’s is desirable
- Design experience in any of Ethernet MAC, DDR, PCIE, DMA, Cache controllers is a big plus, Experience with integrating 3rd party IP’s is desirable
- Scripting experience (Python, Perl, TCL, shell programming) highly desirable
- Experience with formal verification tools is a plus
- Experience with emulation is a plus
- Written and verbal communication skills