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Google Senior Mixed-Signal Design Verification Engineer United States, California, Mountain View 663366076
27.01.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience leading digital verification using SystemVerilog for ASIC designs.
- Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments.
Preferred qualifications:
- Experience in creating detailed block-level design verification strategies and plans.
- Experience creating or using verification components and environments in methodology (UVM, VMM, OVM).
- Experience in RTL, low power (e.g., Unified Power Format or Common Power Format), gate level (GLS) and formal verification techniques.
- Experience working with mixed signal (e.g., Analog Mixed Signal and Digital Mixed Signal) designs and mixed mode verification.
- Knowledge of analog design basics and experience writing SystemVerilog models of analog blocks using advanced techniques (real-number modeling (RNM), Verilog-AMS, etc.).
- Proficiency in one or more scripting languages (Python, etc.)
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