Microsoft Senior Engineer Logic 

India 

656768758

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionateengineers to help achieve that mission.

the ability to deploy new offerings and hardware infrastructure on time in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, theloud Compute Development Organization (Cand sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions,and industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure.

an experienced DDR Logic Design Engineerto join the team.

• BS/MS in Electrical Engineering, Computer Engineering or Computer Science

• 4 -5 years ofDDR4 or DDR5 experience

• High speed digital design experience

• Knowledge of the logic design flow including RTL coding, RTL simulation, synthesis, timing constraints, timing closure

Additional Preferred:

• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting,etc).

• proficiencyin Computer Architecture, Digital Design, CPU/SoC design principles as part of CPU, SoC and/or IP development

• Demonstrated experience and knowledge of design clock crossings and power/UPF.

• Ability to write scripts using Perl,Tcl, Python etc.

• Experience in building and integrating any of the IPs such as memory controllers and DDR.

• Experience in building functional fabrics using Coherent and Non-Coherent protocols.

• Familiarity with Industry standard interface protocols such as AXI or CHI.

• Familiarity with Synthesis and STA tools.

• Good verbal and written communication skills.

• Establish micro-architecture for blocks of acutting-edgeDDR memory controller

• Implement the micro-architectureinVerilogfor DDR IP components or integratesub components.

• high quality ofyour design fromthe perspectivesoffunctionality,timing, CDC, RDC,LEC

• Work closely with our multi-disciplinary team

• optimize