Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM IP, SoC
Analyze design timing, area and power to help improve the quality of ARM IP
Develop and deploy new methodologies to improve implementation efficiency and results
Support and develop detailed implementation analysis and data-mining methodologies.
Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.
Converting R&D concepts into real implementation solutions.
Enable our partners to achieve the best possible quality of results.
Required Skills and Experience :
Bachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.
15+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification and IC design flro from RTL to GDS2
The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills.
Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams
Experience working closely in top and block level Synthesis, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh.
“Nice To Have” Skills and Experience :
Knowledge around Arm based CPUs !
Experience with low power design techniques (power gating, voltage/frequency scaling)
Experience with Verilog RTL design.
Experience with ATPG tools/and or production testing.
In Return:
We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!