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What you’ll be doing:
Innovate across the entire VLSI flow to make incremental recovery and optimization fast and seamless. This will primarily involve C++ and includes improving or replacing in-house algorithms for steps such as incremental CTS (clock tree synthesis), incremental scan insertion, power hookup, placement, timing optimization, etc.
Educate RTL teams on best practices that you identify and advance.
Help develop GUIs for design visualization and other tools to boost designer productivity
Over time, this role can expand to other areas of physical design implementation and analysis tools
As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.
What we need to see:
BS or MS in Electrical Engineering (or equivalent experience)
3+ years experience broadly across VLSI, including exposure to synthesis, clocks, DFT, power distribution, timing, and place & route. Previous experience as a physical design engineer would be ideal.
Proficiency in C++
Some familiarity with use of SAT solvers and packages for logic minimization
Insight and interest in boosting design team productivity through intuitive GUIs and APIs
Ways to stand out from the crowd:
Experience with GUI frameworks, especially ImGui or Qt
Background with synthesis and timing tools, including Design Compiler, Fusion Compiler, and PrimeTime
Experience in using AI-coding assistants such as Cursor
Experience with scripting languages such as Python, Perl, or Tcl
Strong communication and interpersonal skills
You will also be eligible for equity and .
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