Cisco Analog/mixed 

United States, Georgia, Atlanta 

652287384

Application window is expected to close 11/8/24

Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.

As a member of the Mixed Signal Design team, you will be a key member of a small, dynamic IC Design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. You will assist in the architecture of behavioural models and IBIS-AMI models of interfaces to productize ultra-deep sub-micron-based CMOS products.

You will lead efforts to develop complex behaviour models of the analog IO development. This will require you to collaborate with packaging and hardware design teams to ensure models accurately represent the device performance. You will also assist applications engineering in model supports.

You will work with other Acacia mixed-signal, System, and Hardware Engineers to collaborate in order to provide optimized, accurate models that will be used for system and signal integrity investigations. In addition, you will have the opportunity to interact with other Acacia groups including digital/DSP design, package design, and module design. The position will require customer interaction in supporting the released models.

You are enthusiastic about modeling high speed AMS circuits and best-in-class products that push the boundaries of what is possible. You are detail oriented, high energy and the driven to get things done and solve difficult problems.

BSEE degree with 12+ years of experience, or equivalent, an MS degree with 8+ years of experience, or equivalent, or a PhD with 5+ years of experience, or equivalent.

You must have experience in Behaviour modeling and simulation:

• High Speed Serial Links utilizing serializers, deserializers, and data converters.
• High Performance Output Drivers
• High Performance Phase Locked Loops and Phase Interpolators
• Programmable Gain Amplifiers
• Equalization techniques (CTLE, FFE, DFE)
• Clock and Data Recovery
• Jitter analysis and attenuation techniques

• Experience with electrical transceiver applications including backplane, optical, and cable communications
• Experience and familiarity of IEEE 802.3 and CEI standards using multiple modulation schemes
• Experience in signal integrity analysis.
• Present examples of leading innovative projects
• Publications
• Software experience with C/C++, ADS, Matlab/Simulink, Cadence (virtuoso), Spectre/APS/SpectreX, mixed signal simulations in AMS, Python