Amazon SOC RTL Design Engineer Hardware Compute Group 

United States, California, Sunnyvale 

651487027

Work hard. Have Fun. Make history.Key job responsibilities
In this role, you work in a team developing SoCs to be deployed in a range of Amazon devices. You will integrate industry standard and custom hardware IP and subsystems into SoCs to accelerate applications in machine learning, computer vision and robotics. You will work closely with System Architects, SoC architects, IP developers and physical design teams to develop SoCs that meets the power, performance and area goals for Amazon devices. You will design the interconnect, and automate the integration flow. You will help define the processes, methods and tools for design and implementation of large complex SoCs. Develop chip level and subsystem level netlists integrating IPs and new design.
- Work with Chip Architects to understand architecture and high-level product requirements.
- Convert Chip Spec into RTL using internal IPs and external IPs.
- Review Architecture and Design of custom IPs for integration into SoCs.
- Design & Develop RTL for Interconnects, Interfaces, Power Management, Clocking, Reset, Test & Debug.
- Develop and implement methodologies for I/O, DFT, Debug, Clocking and Power Management.

- BS degree or higher in EE or CE or CS
- 3+ years or more of practical semiconductor design experience including full-chip and subsystem RTL integration
- Experience in micro-architecture definition from architecture guideline and model analysis
- Experience in RTL coding (Verilog/System Verilog) and debug, as well as performance/power/area analysis and trade-offs
- Experience in closing full-chip and subsystem timing working with synthesis and static timing analysis teams
- Excellent verbal and written communication skills, collaboration and teamwork skills as well as ability to contribute to diverse and inclusive teams

- MS in Computer Engineering/Electrical Engineering or related field
- Design experience in Datapath, flow control, Arbitration, FIFO, DMA , IOMMU, SoC bus architectures, Arteris NOC interconnect, ARM’s AXI/AHB bus architecture & Protocols, Serial interfaces such as PCIe, QSPI, I2C,UART, EMMC, USB. LPDDR controller & Phy IP integration, embedded memory (SRAM, OTP etc;.) Other IP integration such as ADC, PLL, DLL, PVT sensors, GPIO & Debug (Coresight)
- In-depth knowledge of in one or more areas such as CPU, DSP, or programmable accelerators
- SoC bring-up and post silicon validation experience
- Experience with early RTL power analysis
- Experience with gate level testing and multi clock design practices
- Successful tape outs of complex, high-volume SoCs in advanced design nodes
- Experience with DFT tools for scan and BIST insertion
- Experience with using AI tools tools for RTL generation or automation
- Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area