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Qualifications:
Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 3 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 5 years of relevant industry experience.
Experience: Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification.
Experience in verification of design blocks (IP) for system-on-chip (SoC) components.
Experience in system verilog, and/ OVM or UVM based verification methodologies.
Experience in one/more of the following areas PCI_Express, USB, I3C, MIPI and /or AMBA standards (OCP, AXI, AHB etc.).
Knowledge of scripting, SVA.
Knowledge of IO Interconnect is a plus.
Knowledge of considerations for performance, power and cost optimization is desirable.
Expected to be thorough with general verification concepts with System Verilog/OVM/UVM- Writing test cases and making scoreboard/infrastructure changes to the environment.
Ownership/coding/enhancement of functional scoreboards/agents/sequences/monitors.
Knowledge in FPV is good to have.
Responsible for understanding architecture spec and deriving test cases / test plans.
Need to be a key team player, while being highly energetic and motivated, independent and self-driven (with minimal mentoring/handholding)- Expected to define functional coverage/code/hit it through sequence enhancement and newer/directed test.
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