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Apple GNSS Design Verification Engineer United States, California, San Diego 646886726
03.04.2025
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As a GNSS Design Verification Engineer, you will be responsible for pre-silicon RTL verification of our GNSS IP and SoC subsystem. As part of our DV team, you will develop reusable testbench and verification environment deploying the latest methodology, working closely with GNSS and SoC front-end designers and Systems Engineers.
Build block/subsystem/chip level testbench using outstanding DV methodologies. Build verification plan from specification and review with designers and systems engineers. Architect testbench with maximum reusability in mind and build UVM libraries. Generate directed and constrained random tests, debug failures, manage bug tracking, and close coverage. Create and analyze block/subsystem level coverage model and add test cases to increase coverage. Low power verification and formal verification. Improve DV flow and methodologies.
- BS with a minimum of 3 years of relevant experience.
- Experience with Wireless/DSP block/System-on-Chip verification.
- Advanced knowledge of SystemVerilog and in-depth understanding in UVM methodology.
- Solid verification skills in problem-solving, constrained random testing, and debugging.
- MSEE or beyond is preferred.
- Knowledge of SOC subsystem and low power verification experience.
- Experience with SystemVerilog Assertion (SVA).
- Knowledge of scripting (like Shell, Python, and Perl).
- Experience in mixed-signal modeling and simulation
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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