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Google RTL Design Engineer Google Cloud Israel, Tel Aviv District, Tel Aviv-Yafo 641775226
24.07.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
Preferred qualifications:
- Experience with a scripting language such as Python or Perl.
- Knowledge of FPGA, emulation platforms, and SOC architecture.
- Knowledge of high-performance and low power design techniques.
- Knowledge of assertion-based formal verification.
- Knowledge of one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
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