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Apple Sr Legal Project Manager United States, California, Cupertino 641649795
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APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for all phases of design for high performance microprocessors from register transfer language (RTL) to final GDSII delivery. Perform front end implementation tasks such as structured data path design, synthesis, logic equivalence check, and static timing analysis (STA) to ensure design is meeting performance requirements with targeted timing constraints using industry standard timing signoff tools like primetime. Collaborate with RTL team, by analyzing design and providing detailed feedback, to perform feasibility analysis on suggested microarchitectures, including performance, area, timing, power, complexity, and effort. Generate timing constraints for synthesis, place and route (PnR) and STA tools to do the design timing closure. Perform Place and Route (PnR) by using industry standard tool for floor planning, logic placement, clock tree creation, timing, area and power optimization to meet timing, area and power constraints for meeting design spec. Generate and implement Engineering Change Orders (ECOs) to fix timing and power for by using timing closure tool, primetime and place and route tool. Run physical design verification flow and fix layout versus schematic (LVS) and design rule checker (DRC) violations for making sure design is meeting foundry rule requirements using Calibre tool. Run electrical analysis to do static and dynamic voltage analysis, logic equivalence check for design verification post PnR. Collaborate with Computer-Aided Design (CAD) team to develop physical design methodologies to automate flows and improve overall design quality for power, performance and area improvement. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,091 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location.
- Master's degree or foreign equivalent in Electrical Engineering, Electronic Engineering, Computer Engineering or related field and 1 year of experience in job offered or related occupation.
- 1 year of experience with each of the following skills is required:
- Utilizing very-large-scale integration (VLSI) design and experience understanding logic design, data path analysis and digital design flow.
- Experience in floor planning, placement and optimization, clock tree construction, timing analysis, design routing and physical verification, using PnR and PDV (Calibre) CAD tools.
- Experience performing automation, writing scripts and implementing design, using tool command language (TCL) and shell scripting.
- Experience in Power, Performance and Area analysis
- Analyzing Static timing and Static & Dynamic voltage
- Experience in Physical verification, and experience in layout versus schematic checks.
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