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Google SoC RTL Design Engineer United States, California, Sunnyvale 640385633
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience with RTL coding using Verilog/SystemVerilog.
- Experience with industry-standard EDA tools for simulation, synthesis and power analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience in ASIC design with 3 years of experience working on PCIe design.
- Experience interacting with software, system hardware and other cross-functional teams.
- Experience with scripting languages (e.g., Tcl, Python or Perl).
- Experience developing common library RTL modules and working on PCIe verification and bringup.
- Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.
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