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Cisco ASIC DESIGN TEST ENGINEER United States, Georgia, Atlanta 640177422
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The application window is expected to close on 3/10/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Your Impact
As a member of Acacia’s ASIC team, you will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level and set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse.
- You will work with seasoned DFT engineers to implement and verify Design For Test.
- You will also interact with RTL/PD/STA/ATE, collaborating with them for a successful tape out.
Minimum Qualification:
- Typically: Bachelors + 7 years of related experience, or Masters +4 years of related experience, or PHD + 1 years of experience in ASIC DFT flows and implementation.
- Prior experience implementing scan control logic in RTL
- Prior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVT
- Prior experience with Synopsys/Mentor DFT tools
Preferred Qualifications:
- Experience with scan compression and scan partitioning
- Experience with MemoryBIST, eFuse, Repair and yield improvement techniques
- Experience with JTAG Boundary Scan Insertion AC/DC
- Experience with Clocking architecture during various ATPG modes such as: Intest and Extest
- TCL scripting experience to automate DFT flows
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