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Key job responsibilities
- Use and/or build bit accurate C models
- Evaluate block and sub-systems for testability/verifiability
- Write comprehensive block and system level testplans
- Build assertions, traffic generators and scoreboards
- Execute testplans and perform rigorous debug
- Bachelor's degree in Electrical / Computer Engineering or related field
- 6+ years experience in digital verification, preferably in image processor, SoC/Interfaces
- 3+ years of experience in C/C++ and scripting (Python or TCL)
- 6+ years experience in System Verilog or UVM
- Master's or PH.D in Computer Engineering
- 8+ years of experience in digital verification, preferably in areas of image processing.
- Familiarity with formal verification techniques
- Lab debug experience and/or FPGA debug
- Strong written and verbal skills
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