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Apple Front-End Implementation Synthesis Engineer United Kingdom, England, St Albans 638907891
18.11.2024
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Description
Candidates will be responsible for PPA optimisation of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the outstanding GPU’s for the best consumer products.
Minimum Qualifications
- Minimum of BSc in EE.
- Proficient in Verilog and/or System Verilog and scripting languages.
- Understanding and application of physical design and static timing analysis principles.
Preferred Qualifications
- Familiarity with DFT insertion;
- Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level;
- Experience implementing ECO's for functionality and timing.
- Experience with physical synthesis, including logic and PPA optimisation techniques.
- Ability to analyze critical paths and guide RTL designs to efficient solutions.
- Experience using logic equivalence tools for RTL and Gate-level designs.
- Collaborate optimally with IP teams spanning multiple sites.
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