High speed design experience with extensive knowledge in PCB stack-ups and topologies
Experience in working alongside a chip packaging team . Able to influence and advise on the pinout of SoC's based on PCB analysis efforts including cost optimization, feasibility and trade-off analysis
Experienced in escape routing analysis of high density SoC's and able to provide estimates of the IO count that can be routed with a particular stack-up and design rule set
Detailed knowledge of Signal Integrity analysis of high and Power Integrity techniques from both board design and chip packaging perspectives
Detailed knowledge of embedded system board design, designing with complex LSI devices such as FPGAs, demonstrating an understanding of various high speed IO interface standards such as PCIe and DDR
Desirable Skills and Qualities
The following skills are not essential for this role, but experience in any of the following areas would enhance the application:
Experience in using Cadence CIS, Mentor PADs Layout, Allegro PCB design suite and Hyperlynx tools
Experience of automating: decoupling capacitor optimization, DCR, SI, IC placement optimization etc
Enjoys collaborating and working in a team environment.