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Google Physical Design Lead Static Timing Analysis United States, California, Sunnyvale 635373703
20.11.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
- 10 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).
- Experience with Electronic design automation (EDA) tools (i.e. Primetime, Tempus, Timevision, STAR-RC) and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk).
Preferred qualifications:
- 15 years of experience in the domain of static timing analysis.
- Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Knowledge of semiconductor device physics and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and full-chip static timing topics, including clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification.
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