Amazon Sr ASIC Manager Annapurna Labs 

United States, Texas, Austin 

630458693

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.Key job responsibilities
Driving architectural closure and ensuring specifications coherency with product definition and timelinesOwn development process and chip development methodologies ensuring robust, efficient, high quality design- Drives vendor engagement methodologies
- Owns external IP engagements, driving decisisons and engagements
- IP/ASIC vendor point of contact, owns delivery schedule, drives escalationsOwns overall SOC quality and schedule
- Drive design, implementation and verification closure
- Own reviews and review methodology within the development
- Owns and drives periodic reviews with leadershipDrive and own cross discipline interfaces and activities
- Including SOC org internal teams- Vendors and external IP providersOwns SOC quality and represents SOC team for post silicon life of the SOC/Project
- Post-Silicon Health: Managing chip bring-up readiness, debug planning, and performance/functionality validation strategies
- ATE and Production Test: Coordinating the creation and implementation of efficient production test methodologies to ensure high-quality chip manufacturing
- Provide leadership with SOC quality and production risk assessments
Diverse Experiences
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- Deep SOC architectural, micro architectural, chip design, verification and physical design understanding.
- Experience and deep knowledge in all stages of SOC design from definition to post silicon
- Experience with SOC post silicon validation activities
- 5+ years in either design or verification technical lead and owner of a major block or sybsystem
- 2+ successful tape outs as a major block or subsystem design or verification owner
- Proven experience leading across teams and across disciplines
- Proven experience with program management

- Previous knowledge with Machine learning acceleration SOC architecture
- Higher level degree in computer science or electrical engineering