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Apple Semi-Custom Physical Design Engineer United States, Massachusetts, Boston 626898447
04.04.2024
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Key Qualifications
- - Significant Physical Design experience on mixed-signal and/or SOC designs
- - Deep knowledge of industry standards and practices in Physical Design, including physically aware synthesis, Floor-planning, and Place & Route
- - Deep knowledge or experience with digital signal processing filters design, analog-on-top mixed signal physical and timing interface implementation techniques, and a passion to pursue out-of-the-box physical implementation techniques to achieve uncompromised design goals
- - Validated experience in developing and implementing Power-grid and efficient Clock Distribution Networks
- - Significant understanding of all aspects of physical construction, Integration, Design-For-Test (DFT), and Physical Verification
- - Confirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to collaborate with logic design teams for timing fixes. Power user of industry standard Synthesis, Physical Design, Timing & Power Analysis tools
- - Deep understanding of scripting languages such as Perl/Tcl
- - Deep understanding and knowledge of STA methodology, constraints, and tools
- - Solid understanding of Physical Design Verification methodology to debug LVS/DRC issues at block level
Description
As a Semi-Custom Physical Design engineer, you will excel in all phases of Physical Design of sophisticated Analog Mixed Signal designs from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to the following:- Generate block level static timing constraints.- Build block level floorplan including pin placement and power grid.- Develop and validate advanced low power clock distribution network.- Perform block level place and route and close the design to meet timing, area and power constraints.- Generate and Implement ECOs to fix timing, noise and EM IR violations.- Run Physical Design verification flow at block level and to provide guidelines to fix LVS/DRC violations.- Participate in establishing accurate CAD and Physical Design methodologies by construction designs.- Assist in flow development for Analog-On-Top integration.- Crafting sophisticated layout for mixed signal, and analog circuits in deep sub-micron CMOS technologies.
Education & Experience
Bachelors of Science in Electrical Engineering and 10+ years experience preferred
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