Share
Key job responsibilities
- Use and/or build bit accurate C models
- Evaluate block and sub-systems for testability/verifiability
- Write comprehensive block and system level testplans
- Build assertions, traffic generators and scoreboards in SystemVerilog and UVM
- Execute testplans and perform rigorous debug
- Bachelor's degree in Electrical / Computer Engineering or related field
- 5+ years experience in digital verification, preferably in image processor, SoC/Interfaces
- 3+ years experience in C/C++ and scripting (Python or TCL)
- 5+ years experience in System Verilog or UVM
- Master's or PH.D in Computer Engineering
- 8+ years experience in digital verification, preferably in areas of image processing.
- Familiarity with formal verification techniques
- Lab debug experience and/or FPGA debug
- Strong written and verbal skills
- Familiarity and experience with gate level simulations
- Familiarity and experience with UPF low power simulations
These jobs might be a good fit