Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in ASIC physical design and methodologies in advanced process nodes.
Experience driving place and route on designs using industry standard EDA CAD tools (including command execution, debugging, and custom technique development via Tcl or GUI).
Preferred qualifications:
Master's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience
Experience in the complete physical signoff stack, including timing, PDV, EMIR, package concerns, and power.
Experience with custom physical design, which may include custom datapath design, standard cell design, SRAM/RF design, and “relative placement” design.
Experience measuring and optimizing overall design power.
Familiarity with front-end design and experience leading “PD-aware” design changes to improve PPA or re-use.