Qualcomm Mixed-Signal Senior layout Engineer 

India, Karnataka, Bengaluru 

623038512

Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

• 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

2 to 6 years of industry experience in Mixed-Signal layout design, holding Bachelor’s degree in

To work independently on block levels analog layout design from schematic. Which includes Estimating the Area, Optimizing Floorplan, Routing and Verifications.

Hands on experience in developing layouts for analog blocks like amplifiers, comparator, voltage/current reference circuits, Data converters and Timing Circuits. Experience on RF blocks such as LNA’s, TX, RX, SYNTH and BBF blocks is an additional need.

Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below.

Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Layout Editor, VXL and Calibre RVE.

Good interpersonal skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication, Responsible for timely execution with high quality of layout design.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.